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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays
March 2007
FIN324C
24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays
Features
Ultra-Low Operating Power: ~4mA at 5.44MHz Supports Dual-Display Implementations with RGB or Microcontroller Interface No External Timing Reference Needed SPI Mode Support Single Device Operates as a Serializer or Deserializer Direct Support for Motorola(R)-Style R/W Microcontroller Interface Direct Support for Intel(R)-Style /WE, /RE Microcontroller Interface 15MHz Maximum Strobe Frequency Utilizes Fairchild's Proprietary CTL Serial I/O Technology Available in BGA and MLP packages Wide Parallel Supply Voltage Range: 1.60 to 3.0V Low Power Core Operation: VDDS/A=2.5 to 3.0V Voltage Translation Capability Across Pair with No External Components High ESD protection: >14.5kV HBM Power-Saving Burst-Mode Operation
Description
The FIN324C is a 24-bit serializer / deserializer with dual strobe inputs. The device can be configured as a master or slave device through the master/slave select pin (M/S). This allows for the same device to be used as either a serializer or deserializer, minimizing component types in the system. The dual strobe inputs allow implementation of dual-display systems with a single pair of SerDes. The FIN324C can accommodate RGB, microcontroller, or SPI mode interfaces. Read and write transactions are supported when operating with a Motorola-style microcontroller interface for one or both displays. Unlike other SerDes solutions, no external timing reference is required for operation. The FIN324C is designed for ultra-low power operation. Reset (/RES) and standby (/STBY) signals put the device in an ultra-low power state. In standby mode, the outputs of the slave device maintain state, allowing the system to resume operation from the last-known state. The device utilizes Fairchild's proprietary ultra-low power, low-EMI Current Transfer LogicTM (CTL) technology. The serial interface disables between transactions to minimize EMI at the fundamental serial interface and to conserve power. LV-CMOS parallel output buffers have been implemented with slew rate control to adjust for capacitive loading and to minimize EMI. The serialization bit clock is generated internally to the FIN324C. The minimum bit clock frequency is always great enough to handle the maximum strobe frequency.
Applications
Single or Dual 16/18-Bit RGB Cell Phone Displays Single or Dual 16/18-Bit Cell Phone Displays with Microcontroller Interface Single or Dual Mobile Display at QVGA or HVGA Resolution
Related Application Notes
AN-5058 SerDesTM Family Frequently Asked Questions AN-5061 SerDesTM Layout Guidelines AN-6047 FIN324C Reset and Standby
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays
Ordering Information
Order Number
FIN324CMLX FIN324CGFX
Operating Temperature Package Pb-Free Range
MLP040A BGA42A Yes Yes -30 C to 70 C -30 C to 70 C
Package Description
40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square 42-Ball, Ultra Small Scale Ball Grid Array (USSBGA), JEDEC MO-195, 3.5 x 4.5mm Wide, 0.5mm Ball Pitch
Packing Method
Tape & Reel Tape & Reel
Typical Application Diagram
LCD `A'
WE/PCLK CKS WE/PCLK Data/Control
Baseband / Microprocessor
2 Data/Control 24
FIN324
DS
FIN324
24 WE/PCLK
LCD `B'
Supports optional seconda ry display
Figure 1. Typical Application Diagram
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays
Pin Definitions
Pin I/O Type # Pins Description of Signals
Chip-Level Control Signals M/S /RES IN IN 1 1 LV-CMOS Master/Slave Control Input: M/S=1 MASTER, M/S =0 SLAVE LV_CMOS RESET signal and power-down signal /RES=0: Resets and powers down all circuitry /RES=1: Device enabled LV-CMOS standby signal or output slew rate signal: M/S=1: /STBY M/S=0: RSLEW /STBY=0: Device powered down RSLEW=1: Fast edge rate RSLEW=0: Slow edge rate LV-CMOS parallel / SPI display interface PAR/SPI IN 1 Tells the SerDes it is interfacing with a sub-display with a SPI interface PAR/SPI=1: Parallel Interface PAR/SPI=0: SPI Interface using STRB0(WCLK0) LV-CMOS Input: Master clock source select input. CKSEL(H) IN 1 When M/S=1: CKSEL (passed in serial stream) CKSEL=1: STRB1(WCLK1) Active CKSEL=0: STRB0(WCLK0) Active When M/S=0: This pin must be tied to VDDP. Parallel Interface Signals Master Functionality (Slave Functionality) DP[17:0] DP[6]({SCLK}) DP[7]({SDAT}) CNTL[5:0] {SCLK}CNTL[5] {SDAT}CNTL[4] I/O 6 I/O 18 LV-CMOS data I/O. I/O direction controlled by M/S pin and R/W internal state. DP[6] SPI mode SCLK signal pin when PAR/SPI=0 (Slave Only) DP[7] SPI mode SDAT signal pin when PAR/SPI=0(Slave Only) LV-CMOS data I/O. I/O direction controlled by M/S pin M/S=1: Inputs M/S=0: Outputs In SPI mode, CNTL[5] is SCLK; CNTL[4] is SDAT for master and slave LV-CMOS data I/O. I/O direction controlled by M/S pin. M/S=1: Input M/S=0: Output Functional operation: R/W=1: Read R/W=0: Write LV-CMOS data I/O. Function controlled by M/S pin. M/S=1: STRB0 Input M/S=0: WCLK0 Output LV-CMOS Data I/O. Function controlled by M/S pin. M/S=1: STRB1 Input M/S=0: WCLK1 Output
/STBY(SLEW)
IN
1
R/W
I/O
1
STRB0(WCLK0)
I/O
1
STRB1(WCLK1)
I/O
1
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays
Serial I/O Signals Normal Functionality CKS+(DS+) CKS-(DS-) DS+(CKS+) DS-(CKS-) Supply Signals VDDP VDDS VDDA GND Supply Supply Supply Supply 1 1 1 2 Power supply for parallel I/O and internal circuitry. Power supply for serial I/O. Power supply for internal bit clock generator. Ground Pins: BGA - C1, D2, E3; MLP - center pad, 12 Diff Serial I/O Diff Serial I/O 2 Bi-directional serial I/O CKS+/CKS- when M/S=1 DS+/DS- when M/S=0 Bi-directional serial I/O DS+/DS- when M/S=1 CKS+/CKS- when M/S=0
2
Notes: 1. () Indicate the operation of the pin when operating as a slave device. {} Indicate SPI Mode functionality. ({}) Slave Mode and SPI mode functionality except as noted. 2. Serial I/O signals are swapped on the slave so system traces do not have to cross between master and slave.
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays
Pin Assignments
42 FBGA Package 3.5mm x 4.5mm (.5mm Pitch)
(Top View) 1 A B C D E F G 2 3 4 5 6 A B C D E F G 1 R/W CKSEL (H) GND CKS+ (DS+) CKS(DS-) DS(CKS-) DS+ (CKS+) 2 {SDAT} CNTL[4] {SCLK} CNTL[5] VDDP GND VDDS VDDA /RES
Pin Assignments
3 CNTL[2] CNTL[3] CNTL[1] M/S GND PAR/SPI /STBY (SLEW)
4 STRB0 (WCLK0) STRB1 (WCLK1) CNTL[0] DP[11] DP[2] DP[0] DP[1]
5 DP[17] DP[15] DP[13] DP[9] DP[7] ({SDAT}) DP[4] DP[3]
6 DP[16] DP[14] DP[12] DP[10] DP[8] DP[6] ({SCLK}) DP[5]
Figure 2.
BGA Pin Assignments
33 STRB0(WCLK0)
32 STRB1(WCLK1)
38 {SDAT}CNTL[4]
39 {SCLK}CNTL[5]
37 CNTL[3]
36 CNTL[2]
35 CNTL[1]
34 CNTL[0]
CKSEL(H) CKS+(DS+) CKS-(DS-) VDDS VDDA DS-(CKS-) DS+(CKS+) /RES PAR/SPI M/S
31 DP[17]
30 DP[16] 29 DP[15] 28 DP[14] 27 DP[13] 26 DP[12] 25 VDDP 24 DP[11] 23 DP[10] 22 DP[9] 21 DP[8]
1 2 3 4 5 6 7 8 9 10
40 R/W
Ground Pad
12
13
14
15
16
17
18
19
Figure 3.
MLP Pin Assignments (40 Pins, 6x6mm, .5mm Pitch, Top View)
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
/STBY(SLEW) GND DP[0] DP[1] DP[2] DP[3] DP[4] DP[5] DP[6]{SCLK} DP[7]{SDAT}
20
11
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays
System Control Pins
(M/S) Master / Slave Selection: A given device can be configured as a master or slave device based on the state of the M/S pin. Table 1. Master/Slave M/S 0 1 Configuration Slave Mode Master Mode (/RES, /STBY) Reset and Standby Mode Functionality: Reset and standby mode functionality is determined by the state of the /RES and /STBY signals for the master device and the /RES and internal standby-detect signal for the slave device. The /RES control signal has a filter that rejects spurious pulses on /RES. Table 4. Reset and Standby Modes /RES 0 (PAR/SPI) SPI Mode Selection: The PAR/SPI signal configures STRB0(WCLK0) for SPI mode write operation. STRB1(WCLK1) always operates in parallel mode. Control signals CNTL[5:0] all pass in SPI mode. In SPI mode, the SCLK signal is used to strobe the serializer. SPI mode supports SPI writes only. Table 2. Channel 0 PAR/SPI Configuration PAR /SPI 0 1 M/S=1 MASTER SDAT=CNTL[4] SCLK=CNTL[5] /CS=STRB0 Parallel Mode M/S=0 SLAVE SDAT=DP[7] & CNTL[4] SCLK=DP[6] & CNTL[5] /CS=WCLK0 Parallel Mode 1 1 /STBY(3) X 0 1 Master Reset Mode Standby Mode Operating Mode Slave Reset Mode Standby Mode(3) Operating Mode
Note: 3. The slave device is put into standby mode through control signals sent from the master device. Table 5. Reset and Standby Mode States Pin DP[17:0] CNTL[5:0] STRB[0:1] (WCLK[0:1]) Master Reset / Standby Disabled Disabled Disabled Slave Reset Low Low High Slave Standby Last data Last data High
(CKSEL) Strobe Selection Signal: The CKSEL signal exists only on the master device and determines which strobe signal is active. The active strobe signal is selected by CKSEL and PAR/SPI inputs. Table 3. PAR/SPI PAR /SPI 0 0 1 1 CKSEL Master Strobe Source CNTL[5] STRB1 STRB0 STRB1 Slave Strobe Source DP[6] & CNTL[5] WCLK1 WCLK0 WCLK1
(SLEW) Slew Control: The slew control operates only when in slave mode. This signal changes the edge rate of the DP[17:0], CNTL[5:0], R/W, WCLK1, and WCLK0 signals to optimize edge rate for the load being driven. Master read mode outputs have "slow" edge rates. Table 6. Slew Rate Control /STBY (SLEW) 0 1 Slave M/S=0 "Slow" "Fast"
0 1 0 1
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays
LV-CMOS I/O Signals
System Control Signals
The system control signals consist of M/S, /RES, /STBY(SLEW), PAR/SPI, and CKSEL. For connectivity flexibility, these signals are over-voltage tolerant to the maximum supply voltage connected to the device. This allows these signals to be tied HIGH to either a VDDS or VDDP supply without static current consumption. These signals are all LV-CMOS inputs and should never be allowed to float.
Parallel I/O Signals
The parallel data port signals consist of the DP[17:0], CNTL[5:0], R/W, and STRB1(0)(WCLK1(0)) signals. These signals have built-in voltage translation, allowing the signals of the master and slave to be connected to different VDDP supply voltages.
Serial I/O Signals
CTL I/O Technology
The serial I/O is implemented using Fairchild's proprietary differential CTL I/O technology. During data transfers, the serial I/O are powered up to a normal operating mode around .5V. Upon completion of a data transfer, the serial I/O goes to a lower power mode around VDDS.
Serial I/O Orientation Logic
The serial I/O signal traces should not cross between the master and the slave. The pin locations have been designed to eliminate the need to cross traces. See Table 7, Figure 4 and Figure 5.
Table 7. Serial Pin Orientation Master (M/S=1) (Pad/Pin #) Package MLP BGA CKS+ 2 D1 CKS3 E1 DS6 F1 DS+ 7 G1 CKS+ 7 G1 Slave (M/S=0) (Pad/Pin #) CKS6 F1 DS3 E1 DS+ 2 D1
A
20 19 18 17 16 15 14 13 12
B 6 G F E D C B A 5 4 3 2 DS+ DSCKSCKS+ 1 1

2 3 4 5 6 C D E
21 22 23 24 25 26 27 28 29 30
11
10
M/S
40
39
38
37
36
35
34
33
32
MLP Master
PAR/SPI /RES DS+ DSVDDA VDDS CKSCKS+ CKSEL(H)
9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10
31
30 29 28 27 26 25 24 23 22 21
CKSEL(H) (DS+) (DS-) VDD S VDD A (CKS-) (CKS+) /RES PAR/SPI M/S
MLP Slave
BGA Slave
F G
31
32
33
34
35
36
37
38
39
BGA Master
40
12
13
14
15
16
17
18
19
Figure 4.
BGA Pair
Figure 5.
MLP Pair
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays
Master/Slave READ/WRITE transactions
During a write data transfer, DP[17:0], CNTL[5:0], R/W, and CKSEL are serialized and transmitted by the master to the slave. The slave receives the signals, outputs the data and control signals, and generates either a WCLK0 or WCLK1 pulse based on the value of CKSEL. The CKSEL signal must remain stable throughout the transaction. Read transactions have two phases: The ReadControl Phase, where CNTL[5:0], R/W, CKSEL are transmitted to the deserializer; and the Read-Data Phase, where the DP[17:0] signals of the slave are read and transmitted back to the master device. The slave device generates its own strobe signal for latching in the data. Slave data must be valid prior to the WCLKn signal going HIGH. Master Serializer Operation (Read Control Phase) When the R/W signal is asserted HIGH and the STROBE signal transitions LOW, the Read-Control Phase of the read cycle is initiated. The R/W signal must not transition until the READ cycle completes. For a READ transaction, only eight control signals are captured. The 18 DP bits are ignored during the READ operation. The following sequence must occur for data to be serialized properly: Microcontroller Read Sequence (Read-Control Phase): 1. Selects input strobe source (CKSEL= 0 or 1). 2. CPU sends signals (R/W=1, CKSEL, CNTL[5:0]). 3. STROBE Signal transitions LOW. 4. Captures control bits. 5. Device leaves burst standby mode. 6. Serializes and sends control bits. 7. Serializer turns around serial I/O waiting for data. Slave Deserializer Operation (Read-Control Phase) Microcontroller Read Sequence (Read-Control Phase): 1. Deserializer leaves burst standby mode. 2. Begins receiving valid serial stream. 3. 4. 5. 6. 7. Captures data from serial transfer. Turns around serial I/O. Internally decodes that this is a READ transaction and the WCLK to use. Outputs control signals, 3-state DP data bus. Outputs falling edge of WCLK pulse.
Slave Serializer Read Operation (Read-Data Phase) The slave serializer is enabled on the tail end of the Read-Control Phase of operation. The operation of the serializer is identical to the master serialization except that the strobe signal is generated internally and only the data bits DP[17:0] are captured. Microcontroller Read Sequence (Read-Data Phase): 1. Display device outputs data onto DP bus on falling edge of WCLK. 2. Captures parallel data on generated rising edge of WCLK signal. 3. Serializes data stream. 4. DP signals are sent. 5. CNTL signals are sent as 0. 6. Turns serial I/O around, awaiting next transaction. Master Deserializer Read Operation (Read-Data Phase): Initially the deserializer is in low-power operation. The deserializer wakes up when it detects CKSO+ and CKSO- transition from LOW to normal operating range. Microcontroller Read Sequence (Read-Data Phase): 1. Master deserializer wakes up when the CKSI+ and CKSI- signals reach valid levels. 2. Begins receiving valid serial stream. 3. Outputs data DP[17:0]. 4. Turns serial I/O around and goes to burst standby mode. 5. Processor asserts rising edge of strobe signal to capture data.
SPI WRITE transaction
SPI mode is activated by asserting the PAR/SPI signal low on both the master and slave device. A SPI write is only performed when CKSEL=0. During a SPI transaction, SCLK must be connected to CNTL[5] and is the strobe source for serialization. SDAT is assumed to be on CNTL[4] and all of the remaining control signals and STRB0 are serialized. STRB0 should be connected to the SPI mode chip select. On the rising edge of SCLK, all eight control signals (CNTL[5:0], R/W, CKSEL) are captured and serialized. The data signals are not sent. The /CS signal on STRB0 is captured in bit position CNTL[5]. The deserializer captures the serial stream and outputs it to the parallel port. As shown in Table 2, SDAT and SCLK are output on multiple pins. The DP[7] and DP[6] connections can be used for displays with dual-mode operation and the data pins are multiplexed with the SPI signals. CNTL[5] and CNTL[4] signals can be used when the signals are not multiplexed.
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
Application Diagrams
Baseband Processor
VDDP1 VDDS/A VDDP2 VDDS/A
C2
E2
F2
C2
E2
F2
VDDP VDDS/A /CS PCLK R,G,B[5:0] Hsync_D/C Vsync SD OE RESET
VDDP1
VDDP VDDS/A WCLK0 A4 WCLK1 B4 DP[17:0] CNTL[0] CNTL[1] G1 CKS+ CNTL[2] F1 CKS- CNTL[3] CNTL[4] D1 DS+ E1 DSCNTL[5] R/W M/S PAR/SPI SLEW E3 D2 /RES C1 H
D4:G6 C4 C3 A3 B3 A2 B2 NC A1 NC D3 F3 G3 G2 B1
VDDP2
A4 B4 D4:G6
STRB0 STRB1
Sub-Display Data [7:0] D/C /CS RESET P/S R/W Main Display PCLK R,G,B [5:0] Hsync Vsync SD OE
GPIO /STBY /RES CKSEL
DP[17:0] C4 CNTL[0] C3 CNTL[1] D1 A3 CNTL[2] CKS+ E1 B3 CKSCNTL[3] A2 CNTL[4] G1 DS+ B2 F1 CNTL[5] DSA1 R/W D3 M/S
F3
G3 G2 B1
PAR/SPI /STBY /RES CKSEL
Edge Rate Control Option SLEW must be connected to VDDS or GND for low power.
E3 D2 C1
Notes: 1. 2. 3. 4. 5.
Write-only Interface. Assumes BGA die on display. /CS used to strobe sub-display data. PCLK used for RGB mode. Pin numbers for BGA package.
Figure 6.
Dual Display with Parallel RGB Main Display and 6800-Style Microcontroller Sub-Display
Baseband Processor
VDDP1
VDDS/A
VDDP2
VDDS/A
C2
E2
F2
C2
E2
F2
VDDP VDDS/A /WE PCLK R,G,B[5:0] Hsync_ADDR Vsync SD OE RESET /CS GPIO /STBY /RES CKSEL
VDDP1
VDDP VDDS/A WCLK0 A4 WCLK1 B4 DP[17:0] CNTL[0] CNTL[1] G1 CKS+ CNTL[2] F1 CKS- CNTL[3] CNTL[4] D1 DS+ E1 DSCNTL[5] R/W M/S PAR/SPI SLEW E3 D2 /RES C1 H
D4:G6 C4 C3 A3 B3 A2 B2 A1 NC D3 F3 G3 G2 B1
VDDP2
A4 B4 D4:G6 C4 C3 A3 B3 A2 B2 A1 D3 F3 G3 G2 B1
STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CNTL[3] CKSCNTL[4] G1 DS+ F1 CNTL[5] DSR/W M/S PAR/SPI /STBY /RES CKSEL
E3 D2 C1
Sub-Display Data [7:0] ADDR /WE RESET P/S /CS Main Display PCLK R,G,B [5:0] Hsync Vsync SD OE
Edge Rate Control Option SLEW must be connected to VDDS or GND for low power.
Notes: 1. 2. 3. 4. 5.
Write-only Interface. Assumes BGA die on display. /WE used to strobe sub-display data. PCLK used for RGB mode. Pin numbers for BGA package.
Figure 7.
Dual Display with Parallel RGB Main Display and x86-Style Microcontroller Sub-Display
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
Application Diagrams (Continued)
Module 1 Baseband Processor
VDDP1 VDDS/A VDDP2 VDDS/A
F6 SCLK DP[6]
C2
E2
F2
C2
E2
F2
E5 SDAT DP[7]
VDDP VDDS/A /CS PCLK R,G,B[5:0] Hsync Vsync SD D/C SDAT SCLK GPIO /STBY /RES CKSEL
VDDP1
VDDP VDDS/A WCLK0 A4 WCLK1 B4 DP[17:0] CNTL[0] CNTL[1] G1 CKS+ CNTL[2] F1 CKS- CNTL[3] CNTL[4] D1 DS+ E1 DSCNTL[5] R/W M/S PAR/SPI SLEW E3 D2 /RES C1 H
D4:G6 C4 C3 A3 B3 A2 NC B2 NC A1 NC D3 F3 G3 G2 B1
VDDP2
A4 B4 D4:G6 C4 C3 A3 B3 A2 B2 A1 D3 F3 G3 G2 B1
STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] DS+ G1 CNTL[5] DS- F1 R/W M/S PAR/SPI /STBY /RES CKSEL
E3 D2 C1
Sub-Display SCLK SDAT /CS D/C RESET P/S Main Display PCLK R,G,B [5:0] Hsync Vsync SD
Edge Rate Control Option SLEW must be connected to VDDS or GND for low power.
Notes: 1. 2. 3. 4. 5. 6.
Write-only interface (R/W hardwaired LOW). SPI sub-display interface PAR/SPI=LOW for both master and slave. . SCLK connected to CNTL[5]; SDAT connected to CNTL[4]. Shared data pin SDAT; SCLK connections on sub-display. Assumes BGA die on display. Pin numbers for BGA package.
Figure 8.
Dual Display with RGB Main Display and SPI Sub-Display Interface
Module 1 Baseband Processor
VDDP1 VDDS/A VDDP2 VDDS/A
C2
E2
F2
C2
E2
F2
VDDP VDDS/A /CS0 /CS1 DATA[17:0] D/C RESET 0 RESET 1
A4 B4 D4:G6 C4 C3 A3 B3 A2 B2 A1
VDDP1
VDDP VDDS/A WCLK0 A4 WCLK1 B4 DP[17:0] CNTL[0] CNTL[1] G1 CKS+ CNTL[2] F1 CKS- CNTL[3] CNTL[4] D1 DS+ E1 DSCNTL[5] R/W M/S PAR/SPI SLEW E3 D2 /RES C1 H
D4:G6 C4 C3 A3 B3 A2 B2 A1 D3 F3 G3 G2 B1
VDDP2
STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] G1 DS+ F1 CNTL[5] DSR/W M/S PAR/SPI /STBY /RES CKSEL
E3 D2 C1
Sub-Display DATA [17:0] D/C /CS0 RESET 0 P/S R/W Main Display /CS1 DATA[17:0] D/C RESET 1 R/W
NC NC NC
R/W GPIO /STBY /RES CKSEL
D3 F3
G3 G2 B1
Edge Rate Control Option SLEW must be connected to VDDS or GND for low power.
Notes: 1. 2. 3. 4.
R/W interface. R/W signal connected to baseband microprocessor. . Assumes BGA die on display. PAR/SPI connected HIGH to indicate parallel operation. . Pin numbers for BGA package.
Figure 9.
R/W Dual Display with Parallel Microcontroller Main Display and Sub-Display
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
Application Diagrams (Continued)
Module 1 Baseband Processor
VDDP1 VDDS/A VDDP2 VDDS/A
C2
E2
F2
C2
E2
F2
VDDP VDDS/A /RE /WE DATA[17:0] ADDR /CS0 /CS1
A4 B4 D4:G6 C4 C3 A3 B3 A2 B2 A1
VDDP1
VDDP VDDS/A WCLK0 A4 WCLK1 B4 DP[17:0] CNTL[0] CNTL[1] G1 CKS+ CNTL[2] F1 CKS- CNTL[3] CNTL[4] D1 DS+ E1 DSCNTL[5] R/W M/S PAR/SPI SLEW E3 D2 /RES C1 H
D4:G6 C4 C3 A3 B3 A2 NC B2 NC A1 D3 F3 G3 G2 B1
VDDP2
STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] G1 DS+ CNTL[5] DS- F1 R/W M/S PAR/SPI /STBY /RES CKSEL
E3 D2 C1
Sub-Display /RE /WE DATA[7:0] ADDR /CS0 Main Display /RE /WE DATA[17:0] ADDR
/CS1
D3 F3
GPIO /STBY /RES CKSEL0 CKSEL1
G3 G2 B1
Edge Rate Control Option SLEW must be connected to VDDS or GND for low power.
Notes: 1. 2. 3. 4. 5.
Dual display R/W Intel(R) interface. Assumes BGA die on display. GPIO signal used to select READ or WRITE functionality. Connected to CKSEL and R/W. . Displays selected via the chip selects. Pin numbers for BGA package.
Figure 10.
Dual R/W x86-Style Microcontroller Display Interface
Additional Application Information
Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB. Keep all four differential Serial Wires the same length. Do not allow noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential serial wires. Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. Design goal of 100-ohms differential characteristic impedance. Do not place test points on differential serial wires. Use differential serial wires a minimum of 2cm away from the antenna. For additional applications notes or flex guidelines see your sales rep or contact Fairchild directly.
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD TSTG TJ TL
Parameter
Supply Voltage All Input/Output Voltage Storage Temperature Range Maximum Junction Temperature Lead Temperature (soldering, 4 seconds) IEC 61000 Board Level HBM, 1.5k, 100pF HBM, 1.5k, 100pF, Serial I/0 pins MM, 0, 200pF
Min.
-0.5 -0.5 -65
Max.
+3.6 VDDP+0.5 150 +150 +260 15 8.5 14.5 400
Unit
V V C C C kV kV kV V
ESD
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Symbol
VDDA, VDDS VDDP TA
(4)
Parameter
Supply Voltage Supply Voltage Operating Temperature
Min.
2.5 1.6 -30
Max.
3.0 VDDA/S +70
Unit
V V C
Note: 4. VDDA and VDDS supplies must be hardwired together to the same power supply. VDDP must be less than or equal to VDDA/VDDS.
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
DC Electrical Characteristics - LV CMOS I/Os
Values are provided for over-supply voltage and operating temperature ranges unless otherwise specified. Symbol VIH VIL VOH VOL IIN Parameter Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Input Current SLEW=0 IOH = -250A SLEW=1 IOH = -1mA SLEW=0 IOL = 250A SLEW=1 IOL = 1mA -5 Test Conditions Min. 0.7 x VDDP GND 0.8 x VDDP 0.2 x VDDP 5 Max. VDDP 0.3 x VDDP Units V V V V A
DC Serial I/O Characteristics
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol IODH1 IODL1 IODSTBY VSTBY VGO RTERM Parameter Active Output HIGH Source Current Active Output LOW Sink Current Standby Burst Output HIGH Source Current Output Voltage in Standby or Reset Input Voltage Ground Offset Termination Resistor Test Conditions M/S=1, R/W=0,VOS=0.7V M/S=1, R/W=0, VOS=0.7V M/S=1, R/W=0, VOS=1.0V M/S=1, /RST=1, /STBY=0 IOH=-100A Relative to Driver M/S=0, /RST=0 Internal RTERM CKS+(DS+)=0.9V CKS-(DS-)=0.8V 125 150 175 Min. Typ. 1.5 0.8 130 VDDS 0 Max. Units mA mA A V V
Note: 5. Actual application cable is terminated with 150 on both sides.
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
Power Characteristics
Symbol
IDYN_SER
Parameter
Dynamic Current of Master Device Dynamic Current of Slave Device Burst Standby Current of Master Burst Standby Current of Slave Standby Current
Test Conditions
VDDA/S=2.75V, M/S=1, VDDP=1.8V, /STBY=1, /RES=1 VDDA/S=2.75V, M/S=0 VDDP=1.8V, /STBY=1, /RES=1, CL= 0pF 5.44MHz 12.00MHz 15.00MHz 5.44MHz 12.00MHz 15.00MHz
Min.
Typ.
4 7 8 5 8 10 1.1
Max.
Units
mA
IDYN_DES
mA
IBRST_M
VDDA/S=2.75V, VDDP=1.8V, M/S=1, /STBY=1, /RST=1, No STROBE Signal, CL=0pF VDDA/S=2.75V, VDDP=1.8V, M/S=0, /STBY=1, /RST=1, No STROBE Signal, CL=0pF Serializer or Deserializer VDDS/A=VDDP=3.0V, /STBY=0, /RST=1, STRB1=5.44MHz, CL=0pF
mA
IBRST_S
1.8
mA
ISTBY
10
A
AC Operating Characteristics
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
fWSTRB0 fWSTRB1 fRSTRB tR, tF tS1 tH1 tS2 tH2 tS-STRB tSKEW_DS-CKS
Parameter
Write Strobe Frequency Write Strobe Frequency Read Strobe Frequency Input Edge Rates
(6)
Test Conditions
CKSEL=0 STRB0 (PRS1) CKSEL=1 STRB1
Min.
0 0 0
Typ.
Max.
8 15 2 40
Units
MHz MHz MHz ns ns ns ns ns ns
Write Mode Setup Time Write Mode Hold Time READ Mode Setup Time READ Mode Hold Time CKSEL to STRBn Setup Time Allowed DS-CKS Input Signal Skew
DP before STRBn , See Figure 11 DP after STRBn , See Figure 11 R/W, CNTL before STRBn See Figure 12 R/W, CNTL after STRBn See Figure 12 CKSEL before active edge STRBn See Figure 13, Figure 14 Deserializer Mode Max. Internal Oscillator Frequency See Figure 18
(7)
5 15 0 16 50 -150 0 150
ps
Notes: 6. Characterized, but not production tested. 7. Active edge of strobe is the rising edge for a write transaction and the falling edge for a read transaction.
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
AC Deserializer Specifications
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
tR0, tF0
Parameter
Output Edge Rates of WCLK0,WCLK1
Test Conditions
SLEW=0, CL=5pF 20% to 80%(8) SLEW=0; CL=10pF 30% to 70% SLEW=1, CL=5pF 20% to 80% SLEW=0, CL=5pF 20% to 80% SLEW=1, CL=5pF 20% to 80%
(8) (8) (8) (8)
Min.
8
Typ.
Max.
17 12 10
Units
ns
tR1, tF1
Output Edge Rates of R/W, DP[17:0] CNTL[5:0] CNTL[5:0],R/W to Falling Edge of WCLKn DP, CNTL to WCLK0 DP, CNTL to WCLK1 CNTL to WCLKn Data, CNTL to SCLK WCLK0 Pulse Width Low Write Mode WCLK1 Pulse Width Low Write Mode Pulse Width Low of WCLK Read Mode Pulse Width Low of WCLK SPI Mode
8
22 12 17 ns
SLEW=0; CL=10pF 30% to 70% M/S=0(9), See Figure 15 PAR/SPI=1(9), See Figure 15 PAR/SPI=1 , See Figure 15 PAR/SPI=1 , See Figure 17 PAR/SPI=0 , See Figure 16 M/S=0, R/W=0, PAR/SPI=1 See Figure 15 M/S=0, R/W=0, PAR/SPI=1 See Figure 15 M/S=0, R/W=1, PAR/SPI=1 See Figure 17 M/S=0, R/W=0, PAR/SPI=0 See Figure 16
(9,10) (9) (9) (9)
(8)
tCS tPDV-WR0 tPDV-WR1 tPDV-RD tPDV-SPI tPWL-WR0 tPWL-WR1 tPWL-RD tPWL-SPI
0 50 18 200 40 50 18 200 40
4 60 24 224 60 56 20 220 56
ns ns ns ns ns ns ns ns ns
(9,10)
(9,10)
(9, 10)
Notes: 8. Characterized, but not production tested. 9. Indirectly tested through serial clock frequency and serial data bit tests. 10. Pulse width low WCLKn measurements are measured at 30% of VDDP. Measurements apply when SLEW=0 or SLEW=1.
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
AC Data Latencies
Symbol
tPD-WR0 tPD-WR1 tPD-RD tPD-RDC tPD-RDD tPD-SPI
Parameter
Write Latency Write Latency Total Read Latency Read Control Latency Read Data Latency SPI Write Latency
Test Conditions
WRITE Mode, CKSEL=0 See Figure 15 WRITE Mode, CKSEL=1 See Figure 15 READ Mode See Figure 17 READ Mode See Figure 17 READ Mode See Figure 17
(11,14) (11,12)
Typ.(13)
147 111 340 276 84
Max.
Units
ns ns
(11,12)
480
ns ns ns ns
(11,15)
(11,16)
SPI-WRITE Mode See Figure 16
(11,17)
115
Notes: 11. Minimum times occur with maximum oscillator frequency. Maximum times occur with minimum oscillator frequency. 12. Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time across the flex cable and I/O propagation delays. 13. Assumes propagation delay across the flex cable and through the I/Os of 20ns. 14. Total read latency tPD-RD is the sum of the Read-Control Phase latency (tPD-RDC) and the Read-Data Phase latency (tPD-RDD). tPD-RD = tPD-RDC+ tPD-RDD. 15. Read-Control latency is the sum of the delay through the master serializer and slave deserializer, plus flex cable flight times and I/O propagation delays. 16. Read Data latency is the sum of the delay through the slave serializer and master deserializer, plus flex cable flight times and I/O propagation delays. 17. SPI-Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time across the flex cable and I/O propagation delays.
AC Oscillator Specifications
Symbol
fOSC tOSC-STBY tOSC-RES
Parameter
Serial Operating Frequency Oscillator Stabilization Time After Standby Oscillator Stabilization Time After Reset
Test Conditions
Min.
240
Typ.
275 15 30
Max.
310 30 50
Units
MHz s s
VDDA=VDDS=2.75V /RES=1, /STBY Transition VDDA=VDDS=2.75V /STBY=1, /RES Transition
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
AC Reset and Standby Timing
Symbol
tVDD-OFF tSTRB-RES tSTRB-STBY tRES-OFF tVDD-SKEW tVDD-RES tRES-STBY tDVALID
Parameter
Power Down Relative (18) to /RES /RES after last STRBn Standby time after last strobe Master/Slave Reset Disable Time Allowed Skew between VDDP and VDDA/S(21) Minimum Reset Low Time After VDD Stable /STBY Wait Time After /RES /STBY to Active Edge of Strobe
Test Conditions
See Figure 20 M/S=0 or 1, /STBY=1, R/W=0 See Figure 20 M/S=0 or 1, /STBY=1 See Figure 20
(20) (19)
Min.
20 0 200
Typ.
Max.
Units
s ns ns
M/S=1 /STBY=1, /RES= See Figure 20 Figure 19 M/S=0 /STBY=1, /RES= See Figure 19
(22)
15 - 20 20 30
20 +
s ms s s s
M/S=1 /RES=1, /STBY= See Figure 19 M/S=0 /RES=1 See Figure 19
(23)
Notes: 18. Timing allows the device to completely reset prior to powering down. 19. Internal reset on the filter allows assertion prior to completion of read or write date transfer. 20. Timing ensures that last write transaction is complete prior to going into standby. 21. VDDA/S must power up together. VDDP may power-up relative to VDDA/S in any order without static power being consumed. Guaranteed by characterization. 22. /RES signal should be held low for minimum time specified after supplies go HIGH. It is recommended that /RES be held low during the power supply ramp. 23. STRBn must be held off until internal oscillator has stabilized.
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
Typical Performance Characteristics
Setup Time
STROBE DP,CNTL Data tS1
Setup Time
STRBn CNTL,R/W
tS2
Control
Hold Time
STROBE DP,CNTL Data
tH1
Hold Time
STRBn CNTL,R/W Control
tH2
Setup: CKSEL=0 or 1, R/W=0
Setup: CKSEL=0 or 1, R/W=1
Figure 11.
Master Write Setup and Hold Time
Figure 12.
Master Read Setup and Hold Time
tS-STRB
tS-STRB
tS-STRB
tS-STRB
STRB0 STRB1
STRB0 STRB1
CKSEL DP,CNTL Setup: CKSEL=0 or 1, R/W=0
CKSEL
Data
CNTL Setup: CKSEL=0 or 1, R/W=1
Data
Figure 13.
CKSEL Write Setup Time
Figure 14.
CKSEL Read Setup Time
STRBn
STRBn
CKS
CKS
DS
DS
tPD-WRn DP CNTL WCLKn tCSn
tPD-SPI
tPWL-WRn tPDV-WRn
SDAT SCLK tCS tPWL-SPI tPDV-SPI
Setup: CKSEL=0 or 1, R/W=0, PAR/SPI=1
Setup: CKSEL=0, R/W=0, PAR/SPI=0
Figure 15.
Slave Write Mode Timing
Figure 16.
Slave SPI Mode Timing
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
Typical Performance Characteristics (Continued)
tPD-RD STRBn
CKS
DS
tPD-RD C CNTL SLV WCLKn] tCSn tPW L-RD n
tPD-RD D
tPDV-RD n DPSLV DPMSTR Setup: CKSEL=0 or 1, R/W=1, PAR/SPI=1
Figure 17.
Slave Read Mode Timing
CKS+ CKSDS+ DSVDIFF=0 VID/2 VDIFF=0
tSKEW_DS-CKS
Figure 18.
Allowed Differential Input Signal Skew
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
Typical Performance Characteristics (Continued)
VDDP VDDS/A /RES /STBY DP[23:0],R/W STRBn CKS DS Deserializer
tVDD-SKEW tVDD-RES tRES-STBY Standby Mode Dynamic Mode Valid Data
tDVALID
OFF
ON
Figure 19.
Power-Up Timing
VDDP VDDS/A /RES /STBY STROBE tRES-OFF Dynamic Mode tSTRB-STBY tSTRB-RES Standby Mode tVDDOFF
Deserializer ON OFF
Figure 20.
Power-Down Timing
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
(DATUM A)
Figure 21.
40-Lead, Molded Leadless Package (MLP)
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 22.
42-Ball, Ball Grid Array (BGA) Package
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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SerDesTM FIN324C -- 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual
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3
PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only.
Rev. I24
No Identification Needed
Full Production
Obsolete
Not In Production
(c) 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.0.5
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